Workshop
on Memory Access Decoupled Architectures and Related Issues 
Organizers
Roberto
Giorgi (University of Siena), Cosimo Antonio Prete (Univeristy
of Pisa) and Jelica Protic (University of Belgrade).
Saturday,
September 8, 2001.
08:55
Opening Remarks
09:00
Session 1
"Multithreading
Decoupled Architectures for Complexity-Effective General Purpose".
Michael Sung, Ronny Krashinsky and Krste Asanovic
"A
Decoupled Architecture for Accelerating Multimedia Applications".
Deependra Talla and Lizy K. John
10:00
Keynote Speach: "Dynamic Program Partitioning Approaches for Clustered
Microarchitectures". Antonio Gonzalez.
11:30
Session 2
"Design
of A Memory Latency Tolerant Processor(SCALT)".
Shimizu, Kazuyuki Miyasaka and Hiroaki Haramiishi
"Source
Code Loop Transformations for Memory Hierarchy Optimizations".
Antoine Fraboulet and Anne Mignotte
"High-level
optimization of energy consumed by real-time applications embedded in
DSP Systems".
Sebastien Pignolo, E, Martin, N. Julien and B. Saget