PhD theses

• Loop Pipelining With Resource and Timing Constraints.
  Fermín Sánchez. UPC/DAC, October 1995.
• Structural Methods for the Synthesis of Asynchronous Circuits from Signal Transition Graphs.
  Enric Pastor. UPC/DAC, February 1996.
• High-level and Logic Synthesis Techniques for Low Power.
  Enric Musoll. UPC/DAC, July 1996.
• Formal Verification and Testing of Asynchronous Circuits.
  Oriol Roig. UPC/DAC, May 1997.
  Click here for abstract.

Master theses

• Síntesis de circuitos asíncronos mediante la traducción de circuitos de sincronización a redes de Petri.
  Marco A. Peña. UPC/DAC, March 1995.

Last modified: September 1997.