Technical Reports

1995

• Hierarchical Gate-Level Verification of Speed-Independent Circuits
  Oriol Roig, Jordi Cortadella and Enric Pastor.
• Mapping BDDs into DCVSL gates
  Jordi Cortadella.
• Synthesizing Petri Nets from State-Based Models
  Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno and Alexandre Yakovlev.
• Register Optimization for Maximum Throughput Loop Pipelining.
  Fermín Sánchez and Jordi Cortadella.
  DAC (Departament d'arquitectura de Computadors),
  Tech. Report Num. RR-1995-10, April 1995.
  Universitat Politčcnica de Catalunya.

1994

• Designing Asynchronous Circuits from Behavioural Specifications with Internal Conflicts
  Jordi Cortadella, Luciano Lavagno, Peter Vanbekbergen and Alexandre Yakovlev.
• UNRET: A transformation-based technique for software pipelining with resource constraints
  Fermín Sánchez and Jordi Cortadella.
• Conservative Symbolic Model-Checking of Petri Nets for Speed-independent Circuit Verification
  Oriol Roig, Jordi Cortadella and Enric Pastor.
• Symbolic model checking of Petri nets for the verification of speed-independent circuits
  Oriol Roig, Jordi Cortadella and Enric Pastor.
• A new Look at the Conditions for the Synthesis of Speed-independent Circuits
  Enric Pastor, Jordi Cortadella and Oriol Roig.

1993

• P-time Unique State Coding Algorithms for Signal Transition Graphs
  Enric Pastor and Jordi Cortadella.
• Polynomial Algorithms for Complete State Coding and Synthesis of Hazard-free Circuits from Signal Transition Graphs
  Enric Pastor and Jordi Cortadella.

1992

• High-Level Synthesis of Asynchronous Digital Circuits: Scheduling Strategies
  Rosa M. Badia and Jordi Cortadella.

Last modified: September 1997