Dr. Thomas Sterling received his Ph.d from MIT in 1984 and has held
research scientist positions with the Harris Corporations's Advanced
Technology Department, the IDA Supercomputing Research Center, and the
USRA Center of Excellence in Space Data and Information Sciences. In
1996 Dr. Sterling received a joint appointment at the NASA Jet
Propulsion Laboratory's High Performance Computing group where he is a
Principal Scientist and the California Institute of Technology's Center
for Advanced Computing Research where he is a Faculty Associate. For the
last 20 years, he has engaged in applied research in parallel processing
hardware and software systems for high performance computing. Sterling
was a developer of the Concert shared memory multiprocessor, the YARC
static dataflow computer, and the Associative Template Dataflow computer
concept and has conducted extensive studies of distributed shared memory
cache coherence systems. In 1994, Dr. Sterling led the team at the NASA
Goddard Space Flight Center that developed the first Beowulf-class PC
clusters including the Ethernet networking software for the Linux
operating system and is an author of the 1999 book, "How to Build a
Beowulf" published by MIT Press. Since 1994, Sterling has been a leader
in the national Petaflops initiative chairing three workshops on
petaflops systems development and chairing the subgroup on the Petaflops
computing implementation plan for the President's Information Technology
Advisory Committee. He is also an author of the book, "Enabling
Technologies for Petaflops Computing" published by MIT Press in
1995. Sterling is the Principal Investigator for the interdisciplinary
Hybrid Technology Multithreaded (HTMT) architecture research project
sponsored by NASA, NSA, NSF, and DARPA involving a collaboration of more
than a dozen cooperating research institutions to develop a dynamic
adaptive latency tolerant Petaflops-scale computer employing
superconductor, optical, and processor-in-memory technologies.

Mario held the position of Adjunct Professor in the Electrical and Computer Engineering Dept. at the University of California, Santa Barbara since 1991 until 1998. His areas of research included computer architecture and real-time processors. He has directed doctoral and master's degree students working on multithreaded architectures, superscalar processors, high performance processors and architectures for real-time systems. He was co-director of the Processor Architecture Research Team.

He graduated with his doctorate from the Electrical and Computer Engineering Dept. at the University of California, Santa Barbara in 1990.  Mario has a MSEE degree from the Univeristy of Kansas, Lawrence, Kansas and an engineer degree (Ingeniero en Telecomunicaciones) form the Universidad Nacional de La Plata, La Plata, Argentina. Mario delivered invited talks at various universities and companies in USA and abroad, he has referee papers for ISCA, MTEAC, and PACT and has been in the program committee for MTEAC98 and 99.

During his appointment at UCSB,  Mario taught two advance architecture classes (ECE594).  He directed three Ph.D. students and one MSEE student. Two of the Ph.D. dissertations were is multithreaded architectures and the third one was in branch prediction techniques.  The master thesis evaluated real-time multithreaded architectures.  Since 9/99 he held the position of  Adjunct Professor in the Computer Engineering Dept. at the University of California, Santa Cruz

Since 1998 Mario has been founder and CEO/CTO of XStream Logic Inc.  XStream Logic is a fabless semiconductor company designing high end microprocessor for network systems.

>From 1993-1998 he has been a director at National Semiconductor Corp. leading the design of future generations of microprocessors. Mario was the chief architect of the x86 family processor design. The first design of the group, NS486SXF, was completed in less than 18 months with fully functional first silicon.  Mario last responsibility at National has been as director of architecture at Cyrix corp. where he was responsible for all future x86 generations.

Mario was a Staff IC Architect at Weitek Corp from 1990 til 1991., functioning as the chief architect and manager of teams designing graphics and high performance RISC processors based on the MIPS and Sparc instruction sets.

>From 1991-1993 he was Senior Scientist at Apple Computer Inc. His job functions included research and consulting in computer architecture. He worked on superscalar processors, multithreading, floating point, real-time systems and object oriented architectures. His special emphasis was on the performance evaluation and optimization of PowerPC and ARM architecture processors based on compiler and operating system requirements.

He was a Senior Engineer at Delco Electronics Corp. from 1984-1990, where he worked on numerous projects. He architected the real-time processor which functions as a engine controller in most GM cars. This processor, TIO, was a multithreaded implementation. He was also the architect of the Motorola 68332 micro-controller co-designed by Motorola and Delco Electronics.

Gordon Bell es actualment "senior researcher" en el grup de investigacio en telepresencia de Microsoft, part del "Bay Area Research Center" (BARC).

El Dr. Bell es gradua al MIT l'any 1957, i ha estat "Professor of Computer Science and Electrical Engineering" a la Universitat
Carnegie-Mellon entre 1966 i 1972, encara que la seva feina principal ha estat a la industria: va treballar 23 anys a Digital Equipment Corporation (DEC) on va ser Vice-President de Recerca i Investigacio. Va ser arquitecte i responsable de molts dels productes de DEC, Encore, Argent, Intel i Sun entre d'altres. Ha estat involucrat en el disseny d'uns 30 microprocessadors, incloent-hi el PDP-1, PDP-4, PDP-5, PDP-6, PDP-11, PDP-16, TSS/8, VAX-11, Encore Multimax, Encore Ultramax i l'Ardent Titan Graphics Supercomputer.

Es autor de 7 llibres i de prop de 100 articles en revistes i congresos. Es membre de varies associacions professionals, com la American Academy of Arts and Sciences (Fellow), American Association for the Advancement of Science (Fellow), ACM (Fellow), IEEE (Fellow and Computer Pioneer) i la National Academy of Engineering.

Ha rebut, entre d'altres, els seguents premis: IEEE Von Neumann Medal, AEA Inventor Award for the greatest economic contribution to the New England region, The 1991 National Medal of Technology i el 1995 MCI Communications Information Technology Award for Innovation.

L'any 1987, la IEEE va crear l'"IEEE Gordon Bell Prize for advances in parallelism" per estimular el treball en processament paral.lel.

Timothy Mark Pinkston completed his B.S.E.E. degree from The Ohio
State University in 1985 and his M.S. and Ph.D. degrees in electrical
engineering from Stanford University in 1986 and 1993, respectively.
Prior to joining the University of Southern California in 1993, he was
a Member of Technical Staff at Bell Laboratories, a Hughes Doctoral
Fellow at Hughes Research Laboratory, and a visiting researcher at IBM
T. J. Watson Research Laboratory.  Presently, Dr. Pinkston heads the
SMART (Superior Multiprocessor ARchiTecture) Interconnects Group in
the Computer Engineering Division of the EE-Systems Department at the
University of Southern California.  His current research interests
include the development of deadlock-free adaptive routing techniques
and optoelectronic network router technologies for achieving
high-performance communication in parallel computer systems---both
massively parallel processor (MPP) and network of workstation (NOW)
systems.  Dr. Pinkston has authored over forty refereed technical
papers and has received numerous awards, including the Zumberge Fellow
Award, the National Science Foundation Research Initiation Award, and
the National Science Foundation Career Award.

Dr. Pinkston is a member of the ACM, IEEE, and OSA.  He has been a
member of the program committee for several major conferences (ICPP,
IPPS/SPDP, SC, PCRCW, MPPOI, LEOS, OC, WOCS) and was the program
co-chair for MPPOI'97.  Currently, he serves as an associate editor
for the IEEE Transactions on Parallel and Distributed Systems.

José Duato Marín es catedrático de universidad del área de Arquitectura y
Tecnología de Computadores de la Universidad Politécnica de Valencia y
Adjunct Professor en The Ohio State University (Estados Unidos). Ha sido
Decano de la Facultad de Informática y Vicerrector de Investigación y
Desarrollo Tecnológico de la UPV. Sus resultados de investigación se han
incorporado en el supercomputador Cray T3E de Cray Research y en el diseño
del nuevo microprocesador Alpha 21364. Es autor del libro "Interconnection
Networks: An Engineering Approach" publicado por la IEEE Computer Society
Press, ha sido editor de la revista IEEE Transactions on Parallel and
Distributed Systems, ha participado en el comité de programa de decenas de
congresos y ha sido invitado para impartir conferencias en varios
congresos y en diversas universidades de Estados Unidos.

Dr. McKee holds a bachelor's degree from Yale University, a
master's from Princeton University, and doctorate from the
University of Virginia. She has worked for Digital Equipment
Corporation (now Compaq), Microsoft, and Intel, and
has held internships at Digital Equipment Corporation's
Systems Research Center and the former AT&T Bell Labs (now
Lucent Technologies Bell Labs). She has taught at the
University of Virginia, the Oregon Graduate Institute, and
Reed College, and is presently a research assistant professor
at the University of Utah, where most of her research focuses
on the design of more efficient memory systems.

Dr. Guang R. Gao received his S.M. and Ph.D. degrees in Electrical Engineering
and Computer Science from the Massachusetts Institute of Technology, in 1982
and 1986, respectively.
Currently he is a professor at the Department of Electrical and Computer Engineering at
the University of Delaware, where he has been the founder and leader of the Computer
Architecture and Parallel Systems Lab.
Prior to that he has been an associated professor of the School of Computer Science,
McGill University, Montreal, Canada.
Prof. Gao's main research interests include high-performance computing systems and
architectures, programming language design and implementation, parallel programming
and parallel processing.

Prof. Gao has many research publications in refereed  conference/workshope proceedings
and journals. He was the Co-Editor of Journal of Programming Languages, and a member of the
Editorial Board  of the IEEE Concurrency journal, and IEEE Transaction on Computers.
He has been a program/general chair, or a member of steering/program/organizingcommittee of many international conferences in his field (e.g.
IEEE International Symposium of High-Performance Computer Architecture (HPCA99,HPCA00),
ACM International Conference on Supercomputing (ICS'95),
ACM/IEEE International Symposium on Microarchitectures (MICRO-95,96,97,98),
IFIP and ACM SIGARCH International Conference on Parallel Architectures and Compilation Techniques
(PACT'94,95,96,97,98,99),
Parallel Architecture and Language Europe (PARLE-91,92,93,94,95),
International EURO-PAR Conference (EURO-PAR'95,96,97,98,99),
Working Conference on Massively Parallel Programming Models (MPPM'93,95,97)
High Performance Computing Symposium (HPCS'95,97),
the International Compiler Construction Conference (ETAC-CC'99,00), and others).

He has edited or co-edited several research monographs
He has served as a Guest Editor on Special Issues for the Journal of Parallel
and Distributed Computing and IEEE Transaction on Computers.
He has served in the organizing committees, program committees or
steering committees in many international conferences or workshops
in his field.
Currently, Dr. Gao is a Distinguished Visitor and a Senior Member
of IEEE CS, and a member of ACM SIGARCH, SIGPLAN and IFIP WG 10.3.

Dr. Gabby Silberman is Program Director for CAS, the Centre for Advanced
Studies, at IBM's Toronto Laboratory.  Previously, he was with the
applications systems technologies department at the IBM T. J. Watson
Research Center in New York.

>From 1980 to 1990, Dr. Silberman was on the faculty of both the Computer
Science and Electrical Engineering Departments at the Technion, Haifa,
Israel, and from 1988 to 1990 he was visiting faculty at the Electrical and
Computer Engineering Department, at Carnegie Mellon University.

During the original Kasparov vs. Deep Blue chess match, and again for the
rematch, Dr. Silberman's group provided the technical infrastructure and
support for the computing and audio-visual systems, both on- and off-site.
In 1997, he also served as Deep Blue team coordinator and liaison to the
Kasparov team.

Dr. Silberman is a member of the Association for Computing (ACM), and
serves as the program director for IBM's sponsorship of the ACM
International Collegiate Programming Contest.  He is also a member of the
International Federation of Information Processing Working Group 10.3, and
a senior member of the Institute of Electrical and Electronic Engineers
Computer Society.  This year, Dr. Silberman was elected to IBM's Academy of
Technology, which recognizes him as one of IBM's top technical leaders.

Dr. Silberman received a bachelor's degree in science and a master's degree
in science from the Technion- Israel Institute of Technology.  He received
a doctorate in computer science from The State University of New York at
Buffalo.

John Taylor was one of the founding employees of QSW having worked
previously for Meiko Limited from 1988. At QSW he is now mainly concerned
with Technical Marketing and in particular Product Strategy and Third Party
Software coordination.

In his time at Meiko he worked as an applications consultant, advising
customers on the exploitation of parallel architectures at both the research
and industrial level. Prior to joining Meiko, John was employed by Marconi
as part of a signal processing algorithm development team.

John was educated in Physics at the University of Warwick, England at both
under and post graduate level, he received his doctorate in 1983 concerning
theoretical studies of oxide glasses. In this capacity he was sponsored by
Pilkington Bros.

Department of Computer Design and Fault Tolerance
University of Karlsruhe, D-76128 Karlsruhe, Germany

Theo Ungerer is a professor of Computer Science at the University
of Karlsruhe, Germany. Previously, he was scientific assistant
at the University of Augsburg (1982-89 and 1990-92),
visiting assistant professor at the University of California,
Irvine (1998-90), professor of computer architecture at the
University of Jena, Germany (1992-1993). Since 1993 he is with
the Department of Computer Design and Fault Tolerance,
University of Karlsruhe.

Ungerer received a Diploma in Mathematics at the Technical
University of Berlin in 1981, a Doctoral Degree at the University
of Augsburg in 1986, and a second Doctoral Degree (Habilitation)
at the University of Augsburg in 1992.

His current research interests are in the areas of processor
architecture, microcontroller design, embedded real-time systems,
parallel and distributed computing.

Hewlett-Packard Laboratories Cambridge

Paolo Faraboschi is a research scientist at Hewlett-Packard
Laboratories Cambridge. He received his PhD degree in
Electrical Engineering from the University of Genoa (Italy)
in 1993 and joined HP Laboratories in 1994.

His main interests include compilers, architectures and tools
for high-performance instruction-level parallelism in
embedded systems.

Paolo is currently project manager for the "Custom-Fit
Processors" (CFP) project at HP Labs Cambridge. For more
technical information about the project you can visit our R&D
pages at http://www.hpl.hp.com/cambridge/projects/cfp

Dr. Jim Dehnert received his BS in Mathematics at Stanford University, and
his Ph.D. in Applied Mathematics (formal language theory) at the
University of California at Berkeley in 1983.  He has worked on
commercial compilers since 1978, including MSL, CMS-2, and Ada at ROLM
Corporation, Cydra Fortran at Cydrome, and C, C++, and Fortran at
Apogee Software and SGI.  He was the architect of the SGI code
generator, and has designed and implemented software pipelining loop
preparation, target description tables, interprocedural alias analysis,
register allocation, etc.  His primary interest is in optimization,
code generation, and computer architecture; he also has interests in
programming methodology and parallelism.

Nirav Kapadia is a Research Scientist in the School of Electrical
and Computer Engineering at Purdue University, where he is heading the
technical aspects of the PUNCH project. His research interests are in the
areas of network-based and wide-area distributed computing, WWW-based computing
portals, predictive application-performance modeling, and resource management
across institutional boundaries. He received the B.E. degree from Maharashtra
Institute of Technology (India) in 1990, and the M.S. and Ph.D. degrees from
Purdue University in 1994 and 1999, respectively.

Burton Smith is Chief Scientist of Cray.  He received the BSEE from
the University of New Mexico in 1967 and the Sc.D. from MIT in 1972.
From 1985 to 1988 he was Fellow at the Supercomputing Research Center
of the Institute for Defense Analyses in Maryland.  Before that, he
was Vice President, Research and Development at Denelcor, Inc. and was
chief architect of the HEP computer system.  Dr. Smith is a Fellow of
both the ACM and the IEEE, and winner of the IEEE-ACM Eckert-Mauchly
award in 1991.  His main interest is general purpose parallel computer
architecture.

Christian Perez is a Research Scientist in he computer science laboratory
(LIP) of ENS Lyon where he received the Ph.D. degree. For more information
visit his personal page.

Chris Koopmans is a Ph.D. student studying with Professor C.
Polychronopoulos at the University of Illinois at Urbana-Champaign. He
received his B.S. in Computer Eng. with highest honors in 1998 from the
University of Illinois. He has worked for Cray Research in the area of
microprocessor and NUMA architecture verification, and Intel Corp.
studying multithreaded code generation. He is currently an NSF fellow
and a research assistant at the Center for Supercomputing Research and
Development, where he has helped develop the infrastructure of the
PROMIS research compiler.  His research is currently focused on thread
partitioning and code generation for multithreaded processors.

Nagel,  Wolfgang E., Prof. Dr., since 1997 Professor at the Institute for Scientific
Computing (IWR) at TU Dresden. Additionally, he is the director of the Center for
High Performance Computing (ZHR), one of the central scientific units of the
Technical University. His research profile covers modern programming concepts
and software tools to support complex compute intensive applications, analysis of
innovative computer architectures, and the development of efficient algorithms
and methods.