Dia	Speaker	Títol	Transp./Articles
7 Oct D6-S103	Mateo Valero Toni Juan	Informació de la linea CAP Presentació del Seminari CAP	N/A
14 Oct	Jordi García	Java for High Performance Computing	Resum, Transp. WWW Links Power Point
21 Oct	Enric Morancho	Split Last-Address Predictor Article presentat al PACT'98	Resum Paper Transp.
27 Oct Dimarts	Michael Lindig	Posibilidades de Realización Física de la PRAM (Parallel Access Random Machine)	Resum Biografia
28 Oct	Jesus Labarta	CEPBA: Proyectos y Promoción del Paralelismo	N/A
4 Nov	Roger Espasa	Instrumentació de binaris amb DIXIE Presentació de la eina DIXIE desenvolupada a la linea CAP	Resum
11 Nov	Jesus Sanchez	Cache Sensitive Modulo Scheduling Article presentat al MICRO-30	Resum Paper
18 Nov D6-S103	Frederic Vila	Introducció a la Lògica Difusa	Resum Power Point Transp.
25 Nov	David Lopez	Widening resources: A cost-effective technique for aggressive ILP architectures Prova per la presentació al MICRO-31	Resum Paper Power Point
3 Dec Dijous	Toni Cortes	Swap compression: a way to increase application performance	Resum
9 Des	Alex Ramirez	Optimización del rendimiento de la cache de instrucciones para aplicaciones comerciales	Resum
16 Des CANVI de DIA	Roger Espasa Nova data per determinar	Advanced Vector Architectures	Resum
20 Gen	Agustin Fernandez	Analisis cuantitativo del SPEC95	Resum Power Point Transp.
3r Cicle de Conferencies del C4
25 Gen de 9 a 13h 26 Gen de 9 a 13h 27 Gen de 9 a 11h	Krste Asanovic MIT	Vector Microprocessors: A Case Study in VLSI Processor Design	Resum Transp. dia 1 Transp. dia 2 Transp. dia 3
Final del primer seminari del 3r Cicle de Conferencies del C4
27 Gen 16 h. C6-E101	Ricardo Baeza	Busqueda en el Web: Desafios y Soluciones	Resum
10 Feb	Venkata Krishnan (Digital)	A Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors	Resum
10 Feb canvi de dia	Xavier Martorell nova data per determinar	Thread fork/join techniques	Resum
17 Feb	Joan Manuel Parcerisa	The Synergy of Multithreading and Access/Execute Decoupling Presentat al HPCA-5	Resum paper
18 Feb 11:30	Trevor Mudge University of Michigan	Instruction Set Architectures	Abstract
18 Feb 16:00	Jim E. Smith University of Wisconsin-Madison	Making Instruction Sets Irrelevant and Improving Performance in the Process	Abstract
19 Feb 11:30	Trevor Mudge University of Michigan	Memories	Abstract
3r Cicle de Conferències del C4
24 Feb de 15 a 18h 25 Feb de 15 a 18h 26 Feb de 15 a 18h	Luiz Andre Barroso Western Research Laboratory DEC	Design and Evaluation of Architectures for Commercial Applications	Abstract Dia 1 PowerPoint Dia 2 PowerPoint Dia 3 PowerPoint
Final del 2on. seminari del 3r Cicle de Conferències del C4
10 Mar	Pedro Marcuello	Speculative Multithreaded Processors Basat en l'article presentat al ICS'98	Resum Paper
14 Abr	Antonio Gonzalez	Proyecto MHAOTEU: Memory Hierarchy Analysis and Optimization Tools for the End-User	Resum
20 Abr 17:00 D6-S103	Skevos Evripidou Department of Computer Science University of Cyprus	Hardware and Software tools for Parallel Processing	Abstract
5 mai	Jesús Corbal	Command Vector Memory Systems: High Performance at Low Cost Presentat al PACT'98	Resum paper
12 mai	Cristina Barrado	La herramienta Ictíneo: navegando entre alto nivel y bajo nivel	Resum
19 mai	Sanjay Patel	Delivering Instruction Bandwidth using a Trace Cache	Abstract Biografia transpas
26 mai	Sergi Girona	Promenvir: Una eina d'analisis estadistic de dades desenvolupada al CEPBA	Resum
2 jun	Alex Ramirez	Optimitzacio del rendiment de processadors superescalars mitjancant la cooperacio de mecanismes Software i Hardware Proyecto de tesis	Resum
9 jun	Daniel Jimenez	Ordenación en computadores de altas prestaciones Article presentat al ICS 99	Report
14 Jun dilluns	Trevor Mudge University of Michigan	Smart Register Files	Resum
16 Jun 11:00	Daniel Ortega	Increasing Effective IPC by Exploiting Distant Parallelism Article presentat al ICS 99	Article
23 jun ajornat fins setembre	Josep Llosa	Modelo de area y tiempo para bancos de registros multipuerto y bancos de colas	Resum Report
29 jun ajornat	Mateo Valero	The Future of Vector Processors Keynote del ISHPC'99	PowerPoint
6 jul 11:30	Christian Perez ENS-LYON	A multithreaded runtime environment with thread migration for data-parallel compilers	Resum
7 jul 15:30	Rajkumar Buyya	Architecture Alternatives for Single System Image Clusters	Resum Biografia
13 jul dimarts	Josh Fisher HP Laboratories	The Mass Customization of Instruction-set Architectures	Resum PowerPoint
21 jul	Yale N. Patt	No sabem el titol	Ajornat
30 jul divendres	Josep Torrellas Computer Science Department University of Illinois at Urbana-Champaign, USA	Upcoming Architectural Advances in Distributed Shared Memory Machines and Their Impact on Programmability	Resum
30 ago dilluns	Daniel A. Connors University of Illinois at Urbana-Champaign, USA	Compiler-Directed Elimination of Dynamic Computation Redundancy	Resum Biografia Transpas(pdf)