Per Larsen is a PhD student at the Dept. of Informatics, Technical University of Denmark. He got his Masters degree from the Technical University of Denmark in 2005. His research interests include software development, programming languages and parallel programming.

Israel Koren is a Professor of Electrical and Computer Engineering at the University of Massachusetts, Amherst and a fellow of the IEEE. He has been a consultant to companies like IBM, Analog Devices, Intel, AMD and National Semiconductors. His research interests include Fault-Tolerant systems, secure cryptographic devices, VLSI yield and reliability and Computer Arithmetic. He publishes extensively and has over 200 publications in refereed journals and conferences. He is the author of the textbook "Computer Arithmetic Algorithms," 2nd Edition, A.K. Peters, Ltd., 2002, a co-author of the textbook "Fault Tolerant Systems," Morgan-Kaufman, 2007. He co-founded in 2004 and co-organized the annual workshop on Fault Diagnosis and Tolerance in Cryptography - FDTC, which has become the main conference for presenting new fault injection attacks and countermeasures.

Enric Musoll graduated in computer science from the Polytechnic University of Catalonia at Barcelona (European Union) in 1993 and received the PhD in computer science from the same university in 1996 on the topic of low-power design. Since then, Enric has held industry positions in computer architecture, design and verification in National Semiconductor Corp. and in several start-up companies. Enric is currently co-founder of ConSentry Networks, where he has been instrumental in the design, tape-out and bring-up of the company's family of massive multi-core packet processors. His research interests include high-level synthesis techniques for low power and low-power high-performance computer architectures. Enric holds 20 granted patents and 23 publications in peer-reviewed international conferences and journals.

Doug Burger is a Principal Researcher and manager of the Computer Architecture Group at Microsoft Research. He is currently on leave from the University of Texas at Austin, where he is a Professor of Computer Sciences and Electrical & Computer Engineering, and where he co-ran the TRIPS project, which developed EDGE architectures and NUCA memory systems. His research interests are in computer architecture, power-efficient computing, novel computing technologies, and compilers. He received the ACM Maurice Wilkes Award in 2006, was named an ACM Distinguished Scientist in 2008, and is Chair of ACM SIGARCH.

Laura Grigori is a researcher at INRIA and Laboratoire de Recherche en Informatique of Paris-Sud 11 University, in France. Her field of expertise is high performance scientific computing, numerical linear algebra, and combinatorial scientific computing. She has performed research in various well renowned places, as INRIA, University of California at Berkeley and Lawrence Berkeley National Laboratory. She is leading several projects in developing numerical libraries for large scale parallel/multicore machines and she is a co-developer of SuperLU_DIST, a well known parallel solver for large systems of equations.

Hillery Hunter is a Research Staff Member in the Exploratory Systems Architecture Department of IBM's T.J. Watson Research Center in Yorktown Heights, NY. She is interested in cross-disciplinary research, spanning circuits, microarchitecture, and compilers to achieve new solutions to traditional problems. She has published in the area of embedded DRAM, and is currently engaged with IBM server and mainframe development as DDR3-generation end-to-end memory power lead. She received the Ph.D. degree in Electrical Engineering from the University of Illinois, Urbana-Champaign.

Prof. Nicolau obtained his Ph.D. ('84) from Yale University where he was one of the founding members of the Bulldog/VLIW project. He was on the faculty of Cornell University from 1984 till 1988, when he joined University of California, Irvine as an associate professor and where he is currently a full Professor. He is the author of over 250 peer-reviewed publications including several books, and serves as Editor in Chief of IJPP, the oldest journal in the field of parallel processing.

Prof. David Atienza received his MSc and PhD degrees in Computer Science from Complutense University of Madrid (UCM), Spain, and Inter-University Micro-Electronics Center (IMEC), Leuven, Belgium, in 2001 and 2005, respectively. Currently he is Associate Professor at the Computer Architecture and Automation Department (DACYA) of UCM and Director of the Embedded Systems Laboratory (ESL) at École Polytechnique Fédérale de Lausanne (EPFL), Switzerland. His research interests focus on design methodologies for high-performance embedded systems and Systems-on-Chip (SoC), including new thermal management techniques for Multi-Processor SoCs and 3D stacked processing architectures, dynamic memory management and memory hierarchy optimizations for embedded systems, Networks-on-Chip (NoC) design, novel architectures for logic and memories in forthcoming nano-scale electronics, design of wireless body area sensor networks, and low-power design of embedded systems. In these fields, he is co-author of more than 100 publications in prestigious journals and international conferences, such as, TCAD, Micro, T-VLSI Systems, TODAES, DAC, DATE, etc. Also, he is Associate Editor of IEEE Transactions on CAD (in the area of System-Level Design), Elsevier Integration: The VLSI Journal and IEEE Embedded Systems Letters, as well as part of the part of the Technical Program Committee of DATE and ICCAD, among others conferences. He is an elected member of the Executive Committee of the IEEE Council of Electronic Design Automation (CEDA) since 2008.

Ayose Falcón received his BS (1998) and MS (2000) degrees in Computer Science from the University of Las Palmas de Gran Canaria. In 2005, he received a PhD in Computer Science from the Universitat Politècnica de Catalunya (UPC) under the advisory of Prof. Mateo Valero and Dr. Alex Ramirez. His PhD research included fetch unit optimization, especially branch prediction and instruction prefetching. During his PhD years, Ayose was a summer intern and then a consultant at Intel Microprocessor Research Labs, and worked as teach assistant at UPC for one year. Since 2004, he is a research scientist at HP Labs in Barcelona. His current research interests include simulation and virtualization technologies, disciplines in which he has published several papers and disclosed 6 patents. Daniel Ortega is a Senior Research Scientist at HP Labs. He joined HP in 2003 after finishing his PhD in Computer Architecture at the Universitat Politècnica de Catalunya (UPC). His current research interests include simulation and programming languages. He has previous experience in content processing systems, dynamic optimization, and computer architecture. He is an active member of the Computer Architecture community.

Daniel Angel Jimenez is a native of San Antonio, Texas. He graduated from Tom C. Clarke High School in 1987. He received his B.S. in Computer Science and Systems Design from the University of Texas at San Antonio in 1992 and, under the guidance of Hugh B. Maynard, his M.S. in Computer Science from UTSA in 1994. In 1996, Daniel joined the faculty of the Department of Rehabilitation Medicine at the University of Texas Health Science Center at San Antonio as an instructor where he conducted research on computer-aided design of prosthetic devices. He later returned to graduate school and, under the guidance of Calvin Lin, received his Ph.D. in Computer Sciences from the University of Texas at Austin in 2002. From 2002 through 2007, Daniel was an assistant professor in the Department of Computer Science at Rutgers. In 2005 Daniel took sabbatical leave from Rutgers, joining Mateo Valero's group at the Technical University of Catalonia (UPC) in Barcelona, Catalonia, Spain. In 2008 he was promoted to associate professor with tenure at Rutgers. Having accomplished much at Rutgers but feeling the desire to come home, Daniel returned to Texas and is now an associate professor with tenure in the Department of Computer Science at the University of Texas at San Antonio. Daniel's current research interests include microarchitecture and low-level compiler optimizations. He was awarded an NSF CAREER grant to continue his work on branch prediction.

Avi Mendelson is a principal engineer in Intel's Mobile Platform Group in Haifa, Israel, and adjunct professor in the CS and EE departments, TechnionIsrael Institute of Technology. He received his B.Sc. and M.Sc. degrees from the Technion, Israel Institute of Technology and his Ph.D. from the University of Massachusetts at Amherst. Avi has been with Intel for 7 years. He started as senior researcher in Intel Labs, later he moved to the Microprocessor group where he served as the CMP architect of Intel Core Duo. Avi's work and research interests are in computer architecture, low power design, parallel systems, OS related issues and virtualization.

Gabor Dozsa received his MSc and PhD degrees in computer science at the Lorand Eotvos University of Sciences in Budapest in 1996 and 2003, respectively. From 1996, he had a research fellow position in the Laboratory of Parallel and Distributed Systems at the Computer and Automation Research Institute of the Hungarian Academy of Sciences. In 2000, he was promoted to deputy head of the Laboratory. In 2004, he accepted a post doctoral assignment at the IBM T.J Watson Research Center in New York. In 2005, he became Research Stuff Member in the Blue Gene System Software Group and he currently works on the messaging software stack of Blue Gene supercomputers. He is author or coauthor of more than thirty refereed conference and journal papers and book chapters in the field of parallel, distributed and grid computing.

Emery Berger is an Associate Professor in the Department of Computer Science at the University of Massachusetts Amherst. He graduated with a Ph.D. in Computer Science from the University of Texas at Austin in 2002. His research spans programming languages, runtime systems, and operating systems, with a particular focus on systems that transparently improve reliability and performance. He is the creator of various widely-used software systems including Hoard, a fast and scalable memory manager that accelerates multithreaded applications. His honors include a Microsoft Research Fellowship (2001), an NSF CAREER Award (2003), a Lilly Teaching Fellowship (2006), and a Best Paper Award at FAST 2007. Professor Berger is the General Chair of the Memory Systems Performance and Correctness 2008 workshop, and serves as an Associate Editor of the ACM Transactions on Programming Languages and Systems.