Adriana Zubiri is a developer in the DB2 UDB Team in the IBM Toronto Lab. She holds a MSc in computer science from the University of Alberta, Canada. She has 7 years of experience working with DB2 and more than 10 years in the database field. Since she joined IBM she has worked extensively with customers and specialized in the performance area. Her area of expertise is join processing and she is the current join expert in the DB2 Runtime team.

Guri Sohi received a Ph.D in Electrical and Computer Engineering from the University of Illinois, and has been a faculty member at the University of Wisconsin-Madison since 1985. Sohi's research has been in the design of high-performance computer systems. Topics that he has investigated in the past or continues to investigate include include dynamically-scheduled instruction-level parallel processors, out-of-order execution with precise exceptions, non-blocking caches, decentralized microarchitectures, speculative multithreading, computation reuse, memory dependence speculation and prediction, value degree of use prediction. He received the 1999 ACM SIGARCH Maurice Wilkes award "for seminal contributions in the areas of high issue rate processors and instruction level parallelism". At the University of Wisconsin he was selected as a Vilas Associate in 1997 and won the WARF Kellett Mid-Career Faculty Researcher award in 2000.

Ras Bodik is an Assistant Professor at UC Berkeley. Previously, he was at University of Wisconsin. His current projects explore how run-time information can aid program analysis in solving problems of computer architecture, software engineering, and dynamic compilation. BAFL is joint work with Brian Fields and, in part, with Shai Rubin, Mark Hill, and Mary Vernon (University of Wisconsin).

Juan-Antonio Carballo is currently with IBM's Austin Research Laboratory, where he is leading Communication Systems and Strategy research, including all aspects of system-level and mixed-signal design. He is the driver of IBM's research in adaptive communications hardware, and has won an IBM Division award for his work in high-speed energy-efficient communications chips. He has filed 16 patents and has over a dozen publications in low-power design, mixed-signal design, communications systems, design economics, and electronic design management. He is the Chair of the ITRS Design Group and the co-Chair of the VSIA Implementation Group. He has been on the committee of 6 symposiums and conferences, and is the General Chair for Electronic Design Processes 2004 in Monterey, CA. His prior work experience includes stays at Digital Equipment (currently HP/Compaq) and LSI Logic. Juan-Antonio holds a Ph.D. in Electrical and Computer Engineering from the University of Michigan, an M.B.A. from the Collège des Ingénieurs (Paris), and an M.S. in Telecommunications Engineering from the Universidad Politécnica de Madrid.

Yanos received the BSc degree from Oakland University in 1991 and the ME degree from Cornell University in 1992. He was awarded a PhD degree in 1999 from the University of Wisconsin-Madison in Electrical Engineering. He contributed to the research and development of high performance processors while employed at HP, Compaq and Intel. As of January 2000 Yanos is with the Department of Computer Science at the University of Cyprus. His main research interests lie in the area of Computer Architecture with particular emphasis on high performance microprocessors, program behavior, prediction, speculation, and power aware computing.

Dr Michael O'Boyle is currently a Reader in the School of Informatics at the University of Edinburgh,  an Honorary Lecturer at the University of Manchester and, from Jan 1st 2001, an EPSRC Advanced Research Fellow. He was formerly a SERC Postdoctoral Research Fellow, a Research Associate at the University of Manchester, a Visiting Research Scientist at IRISA, Rennes, and a Visiting Research Fellow at the Institute of Software Development and Parallel Systems, University of Vienna. He was recently appointed as a Visiting Scholar at Stanford University. His main research interests are in adaptive compilation, formal program transformation representations, the compiler impact on embedded systems and automatic compilation for parallel single-address space architectures. He has published over 40 papers in international journals and conferences in this area.

Peter Van Roy is member of the Dept. of Computing Science and Engineering at the the Université catholique de Louvain in Louvain-la-Neuve. He has worked in logic language implementation, showing that Prolog can be compiled with the same run-time efficiency as C. He is codesigner (with Seif Haridi and Per Brand) of the distribution model of the Mozart Programming System. With Seif Haridi he has written a comprehensive textbook on modern programming techniques that is being published by MIT Press. He is currently working on tools and techniques for simplifying the development of robust collaborative applications on the Internet.

Nicholas Carter is an Assistant Professor at the University of Illinois at Urbana-Champaign. Prior to that, he was a graduate student at the Massachusetts Institute of Technology, where he worked on the M-Machine project. His research interests include reconfigurable computing, computing with non-silicon devices, and new models of computation.

Mario Nemirovsky has done research in many areas of computer architecture, including simultaneous multithreading, high performance architectures, real-time and network processors. He is the founding CEO/CTO of Kayamba Inc. designing the next generation of stateful processors. Previously, he founded . XstreamLogic, Inc. and architected their high performance SMT network processor. This architecture was capable of running up to 8 threads simultaneously. Before that, he was a chief architect at National Semiconductor and at Weitek. Inc. In 1985 he was a chief architect at Delco Electronics, General Motors (GM) where he architected a GM engine control. This heavily multithreaded real time processor is still used in all GM cars today. He was one of the first to understand the power of multithreading which he termed dynamic multistreaming and first published on this subject in Micro-24 in 1991. He subsequently published results on SMT in HICSS (in 1993 and 1994) and in PACT (in 1995). Mario received his PhD in ECE from UC Santa Barbara in 1990 and was an Adjunct Professor there from 1991 to 1998. Mario holds 23 issued and 12 pending patents.

Wei Li is a Principal Engineer and Manager of Itanium Compiler Development, a multi-site (California USA, New Hampshire USA, Bangalore India, Nizhny Russia) engineering team in Intel's Software and Solutions Group, responsible for the development of Intel Itanium C++/Fortran product compilers. He leads the development of technologies that have delivered compiler performance and quality for enterprise and technical computing systems. He also leads the technical exchanges with compiler vendors, and interacts with customers in application performance tuning, pre-sale and post-sale support activities. He has given presentations on compiling for Itanium at conferences and academic institutions such as ISCA, HotChips, MICRO, Stanford, and UC-Berkeley. He has served on research conference committees, and has published many research papers on compiler optimizations, parallel data mining, and parallel processing. He holds a PhD in Computer Science from Cornell University, and was an Assistant Professor at the University of Rochester and Principal Member of Technical Staff at Oracle Corporation.