Mark D. Hill  is Professor and Romnes Fellow in both the Computer
Sciences Department and the Electrical and Computer Engineering
Department at the University of Wisconsin-Madison. He currently
co-directs the Wisconsin Multifacet project with Prof. David Wood.
Hill is visiting UPC for the 2002-2003 adcademic year.

Hill has made contributions to cache design, cache simulation, translation
buffers, memory consistency models, parallel simulation, and parallel
computer design.  He won an NSF Presidential Young Investigator award
in 1989, was named an IEEE Fellow in 2000 for "contributions to cache
memory design and analysis," and co-won the best paper award in VLDB
2001.

Hill earned a Ph.D. in Computer Science from the University of California
- Berkeley in 1987, an M.S. in Computer Science from Berkeley in 1983, and
a B.S.E. in Computer Engineering from the University of Michigan in 1981.

Alex Veidenbaum received a Ph.D. in computer science from the
University of Illinois at Urbana-Champaign in 1985.  From 1985
till 1994 he was on the research faculty at the Center for
Supercomputing Research and Development at the University of
Illinois working on the architecture and hardware design of the
Cedar multiprocessor system.  From 1994 to 1995 he worked in France
trying to design another supercomputer. He finally settled down in
1995 and became a faculty member, first at the University of
Illinois in Chicago and since 1998 at the University of California
Irvine.

Dr. Veidebnbaum's research interests are in the areas of computer
architecture, compilers, and embedded systems.  He has worked on
compiler-controlled cache coherence, instruction and data prefetching,
interconnection networks, adaptive data caches, compiler
optimization and program restructuring techniques. Another area of
interest is reducing energy consumption through architectural techniques,
for both high-performance and embedded systems. Recent work in this area
focused on I- and D-caches.

James Larus is a Senior Researcher at Microsoft Researcher, where he
leads the Software Productivity Tools group. Prior to moving to
Microsoft in 1997, he was an Associate Professor in the Computer
Sciences Department at the University of Wisconsin-Madison. There, his
research was in the area of programming languages, compilers, and
parallel computation, and he co-led the Wisconsin Wind Tunnel project.
He has a MS and PhD from the University of California, Berkeley and an
AB from Harvard College.

Rich Zippel is the director of the Compaq's Cambridge Research Laboratory in
Cambridge, Massachusetts, where he supervises research in the areas of
mobile/pervasive computing, multimedia management, high performance systems,
and system verification. Prior to joining HP in 2000, Rich was one of the
founders of the School of Computer Science at Israel's Interdisciplinary
Center in Herzliya, serving as Professor of Computer Science. Previously, he
was a research fellow at the IBM Haifa Research Laboratory in Haifa, Israel,
led research projects in scientific computing and programming languages at
Cornell University, and was a Technical Director at Symbolics, Inc. of
Cambridge, Massachusetts where he directed their parallel computing
projects. Dr. Zippel received his Ph.D. at MIT for the development of
probabilistic algorithms - the use of randomization to solve problems that
do not involve random numbers. Subsequently, he was an assistant and
associate professor at MIT leading a research group in VLSI CAD and VLSI
circuit design. He has been a consultant to a number of companies including
serving on United Technologies' Semiconductor Advisory Board, where he
provided advice on the integration of Mostek into UTC and its final sale.

Paolo Faraboschi is a principal research scientist at HP Labs Cambridge,
where he has been leading the "Custom-Fit Processor" project, with a goal to
produce customized high-performance VLIW processors and tools for embedded
systems. Together with STMicroelectronics, the project co-developed the
Lx/ST200 family of VLIW embedded cores, to be used in digital video consumer
products. Paolo received his PhD degree in Electrical Engineering from the
University of Genoa (Italy) in 1993 and joined HP Laboratories in 1994. His
main interests include computer architecture, VLIW processors, compilers and
tools for high-performance instruction-level parallelism in embedded
systems, and - more recently - the computing aspects of digital imaging
systems.

Dr Michael O'Boyle is currently a Reader in the School of
Informatics at the University of Edinburgh,  an Honorary Lecturer at the
University of Manchester and, from Jan 1st 2001, an EPSRC Advanced
Research Fellow. He was formerly a SERC Postdoctoral Research Fellow,
a Research Associate at the University of Manchester, a Visiting
Research Scientist at IRISA, Rennes, and a Visiting Research Fellow at
the Institute of Software Development and Parallel Systems, University
of Vienna. He was recently appointed as a Visiting Scholar at Stanford
University.

His  main research interests are in adaptive compilation,
formal program transformation representations, the compiler impact on
embedded systems and automatic compilation for parallel single-address
space architectures. He has published over 40 papers in international
journals and conferences in this area.

I am currently a third-year Ph.D student working for Jim Smith at UW-Madison.
I received my MSEE at UW-Madison in 2002 (thesis topic was "The Complexity of
Verifying Memory Coherence"). I received my BSEE and BSCompE degrees from
the University of Cincinnati in 2000.

Jose-Miguel Pulido tiene un doctorado corto por Stanford University
(Engineer degree), donde realizo su tesis sobre la transimisión de capas
de vídeo con diferentes prioridades sobre Internet, con el profesor
Fouad A. Tobagi. Tambien posee un máster en computer engineering por la
Universidad de California Irvine (UCI), y es ingeniero de
telecomunicaciones por la UPC. Ha sido becario de "la Caixa" y becario
Balsells.

Actualmente está trabajando con RouteScience Technologies, una empresa
de Silicon Valley líder en el sector de control de rutas. José-Miguel es
coautor de varias de las patentes fundamentales sobre control de rutas
que RouteScience ha registrado. Jose-Miguel trabajó anteriormente en
iBeam Broadcasting, Accenture y Method Software.

Ronny Ronen is the director of the Microarchitecture Research, Intel Labs
in the Intel Israel Design Center. The research group focuses on promoting
microarchitecture innovations to improve performance and reduce power of
future Intel IA32 processor generations. In the past, the group focused on
microarchitecture innovations for high performance - including topics like
ILP improvements, enhanced instruction caching structures, and more.

Prior to his microarchitecture activities, Ronny led the Pentium®
Processor compiler and performance simulation activities in the Intel
Israel Software department (in Haifa). Before that he was involved in
various software projects, most notably the development of software
development tools for the 8051 microcontroller, leading the hosting of
Intel tools on the VAX/VMS environment, leading the iRMX-286 R2.0 OS
development, and leading the development of i860 software development
tools.

Ronny received his B.Sc. and M.Sc. degrees in Computer Science from the
Technion, Israel Institute of Technology, in 1978 and 1979 respectively.
Ronny is an Intel Principal Engineer and a senior member of the IEEE.

Gustav Hållberg is Vice President of Product Management at Virtutech. He has a
background working as a software developer for several years and studied
Engineering Physics at the Royal Institute of Technology, Stockholm, Sweden.
He has been with Virtutech since 1999, when he wrote his Master's Thesis
there.

Alex Veidenbaum received a Ph.D. in computer science from the
University of Illinois at Urbana-Champaign in 1985.  From 1985
till 1994 he was on the research faculty at the Center for
Supercomputing Research and Development at the University of
Illinois working on the architecture and hardware design of the
Cedar multiprocessor system and conducting research on multiprocessor
architecture and compilation.  From 1994 to 1995 he worked in France
trying to design another supercomputer. He finally settled down in
1995 and became a faculty member, first at the University of
Illinois in Chicago and since 1998 at the University of California
Irvine.

Dr. Veidebnbaum's research interests are in the areas of computer
architecture, compilers, and embedded systems.  He has worked on
compiler-controlled cache coherence, instruction and data prefetching,
interconnection networks, adaptive data caches, compiler
optimization and program restructuring techniques. Another area of
interest is reducing energy consumption through architectural techniques,
for both high-performance and embedded systems. Recent work in this area
focused on I- and D-caches.

Dr. Hehl is currently the content manager of the 'Industry Solutions Labs Zürich'. This Industry Solutions Lab is the European executive briefing center of  the Research Division of IBM  and a global meeting place of executives and politicians  with IBM researchers and consultants.

Dr. Hehl started his career as physicist and development engineer at IBM's development laboratory in Böblingen (Germany) where he was for many years responsible for advanced developments and innovation for systems and software. After a sabbatical year as professor for software technology at the Technical University of Dresden, he became the content manager for IBM's European Industry Solutions Lab, first in Stuttgart (Germany), the directly in the IBM Research Lab Zurich. In this function,  he is responsible for the technologies and solutions used to represent actual trends in IBM Research and in the industry.

He holds IBM's 3rd  plateau for patent disclosures.

Liviu Iftode is an Assistant Professor in the Department of Computer
Science,  University of Maryland. He received his Ph.D. in Computer
Science from Princeton University in 1998.  His research interests include
distributed systems, operating systems, networking and pervasive computing.
Most of his work has been conducted with his students in the Distributed
Computing (DISCO) Laboratory (http://discolab.rutgers.edu) at Rutgers
University, from where he is currently on leave.

Liviu Iftode is the vice-chair of IEEE Technical Committee on Operating
Systems and a member of the Editorial boards of IEEE Pervasive Computing
and Distributed Systems Online. More information can be found at
http://www.cs.umd.edu/~iftode.

Michel BENARD is working for HP University Relations and in charge of
several HP Technology Programs with Universities located worldwide. A
typical HP Technology Program addresses an area of global interest in
Research and Development (like Linux, Grid Computing or BioScience) and
includes relations with up to 20 Universities and Public Research
Laboratories. Before working for HP University Relations, Benard held
several R&D, Sales and Management positions for HP and other global Hi-Tech
companies during 20 years

                    Guri Sohi received a Ph.D in Electrical and Computer Engineering from the University of
                    Illinois, and has been a faculty member at the University of Wisconsin-Madison since 1985. He is
                    currently a Professor in the Computer Sciences department.

                    Sohi's research has been in the design of high-performance computer systems. He has co-authored
                    several papers and patents that have influenced both researchers and commercial microprocessors.
                    In the mid 1980s, while most computer architects were investigating in-order processors, he
                    investigated out-of-order processors. His paper "Instruction Issue Logic for High-Performance,
                    Interruptible Pipelined Processors" (in ISCA 1987) articulated a model for a dynamically-scheduled
                    processor supporting precise exceptions, a model that was widely adopted by several
                    microprocessor manufacturers. (This paper, and the journal version in IEEE Trans. on Computers,
                    March 1990, have been referenced by over 120 U.S. patents) His paper
                    "High Bandwidth Data Memory Systems for Superscalar Processors" (in ASPLOS 1992) argued for
                    non-blocking (or lockup-free) caches, and was instrumental in influencing high-end
                    microprocessors to switch from blocking to non-blocking caches. In the early 1990s while other
                    computer architects started investigating out-of-order processors he proposed the concept of
                    multiscalar processors and thread-level speculation in his papers "The Expandable Split Window
                    Paradigm for Exploiting Fine-Grain Parallelism" (in ISCA 1992) and "Multiscalar Processors" (in
                    ISCA 1995). Thread-level speculation and its variants are currently one of the most active areas of
                    research in computer architecture. His paper "Dynamic Speculation and Synchronization of Data
                    Dependences" (in ISCA 1997) introduced the idea of memory dependence prediction, an idea that
                    was adopted by the Alpha processor designs and is being considered by others. His paper "Dynamic
                    Instruction Reuse" (in ISCA 1997) proposed the concept of instruction reuse, another area of active
                    research. He and his students also had the first academic proposal for trace caches. Sohi's research
                    group also developed the Simplescalar simulator, a simulation toolset that is widely used for
                    research and instruction.

                    Sohi has interacted heavily with industry. Over the years he has discussed his research with
                    architects and given talks in design groups at most of the leading microprocessor manufacturers,
                    including Digital Equipment, HaL, Hewlett-Packard, IBM, Intel, MIPS, Motorola, Silicon Graphics, and
                    Sun Microsystems.

                    He edited "25 Years of the International Symposium on Computer Architecture - Selected Papers"
                    published by ACM, and recently co-edited (with Mark Hill and Norm Jouppi) "Readings in Computer
                    Architecture" published by Morgan Kaufmann Publishers.

                    Sohi has graduated 12 Ph.D students, many of whom currently hold academic positions at leading
                    U.S. research universities (Illinois, Maryland, Michigan, Pennsylvania, Purdue, and Toronto). They
                    include five winners of NSF CAREER awards and a winner of a Sloan Research Fellowship. He
                    continues to lead a research group investigating different models for speculative multithreading,
                    approximate programs, value communication prediction and other microarchitectural innovations.

                    He received the 1999 ACM SIGARCH Maurice Wilkes award "for seminal contributions in the areas of
                    high issue rate processors and instruction level parallelism". At the University of Wisconsin he was
                    selected as a Vilas Associate in 1997 and won the WARF Kellett Mid-Career Faculty Researcher
                    award in 2000.

Gabriel Wainer
Dept. of Systems and Computer Engineering
Carleton University (Ottawa, Canada)

Gabriel Wainer recibió la Licenciatura (1993) y el Doctorado (1998, con
Felicitación del Jurado) en Ciencias de la computación, en la  Universidad
de Buenos Aires (Argentina) y la Université d'Aix-Marseille III (France).
Es Assistant Professor en el Departamento de Systems and Computer
Engineering, Carleton University (Ottawa, Canada). Fue Profesor Adjunto en
el Departamento de Computación de la Universidad de Buenos Aires, Argentina
(1997-2000). También fue investigador visitante en el Arizona Center of
Integrated Modelling and Simulation (ACIMS, University of Arizona, Tucson,
AZ, USA) y profesor invitado en el laboratorio LSIS del CNRS (Marseille,
France).

Ha publicado más de 70 artículos en el área de simulación de eventos
discretos, sistemas en tiempo real y sistemas operativos.Es autor de un
libro de sistemas en tiempo real, y de otro de simulación de eventos
discretos. Ha sido Investigador Principal de diversos projyectos (ANPCYT-
Argentina, Usenix Foundation - USA, NSERC, Canadian Foundation for
Innovation, IRIS - Canada, etc.). Fue miembro del Board of Directors y es
el director del comité de estándares de la Society for Modeling Computer
Simulation International (SCS). Coordina un grupo internacional de
estandarización DEVS. Es Editor Asociado de Transactions of the Society for
Computer Simulation International (SCS). Es Director Adjunto del Ottawa
Center of The McLeod Institute of Simulation Sciences.

Para más información: http://www.sce.carleton.ca/faculty/wainer.html

Romualdo Pastor-Satorras got his Ph.D. at the University of
Barcelona. He has been research fellow at Yale University and
research assistant at the Massachusetts Institute of Technology in
Boston. He spent two years as a research fellow at the
International Center for Theoretical Physics (UNESCO) and moved
back to Spain in 2000 as Assistant Professor at the University of
Barcelona. Since 2001 he holds a research scientist  position at
the Universitat Politecnica de Catalunya. He is author of more
than 45 research papers in different areas of non-equilibrium
statistical physics, condensed matter theory, and complex networks
analysis.

Professor Veljko Milutinovic
University of Belgrade

Prof. Milutinovic was responsible for the architecture/design of the
world's first 200MHz microprocessor, for US defence agency DARPA, about a
decade before Intel (in GaAs technology). He published about 50 papers in
IEEE journals and about 20 books (for major publishers in the USA: Wiley,
Prentice-Hall, North-Holland, etc.). For 7 of his edited books, forewords
were written by 7 different Nobel Prize winners, and 3 of his original
books (himself as a single author) were bestsellers for their publishers
in the USA (Wiley, IEEE CS Press, Kluwer). His Ph.D. is from U. of
Belgrade; after that for about a decade he was on the faculty of Purdue
University in the USA (one of the top 5 out of about 2000 USA schools in
electrical and computer engineering). He returned to Belgrade in 1990 (so
as not to miss any of the excitements in that part of the World, during
the decade of 90s). There he continued to do consulting and product
developments for the cutting edge industry in the USA (he has consulted
for Intel, Honeywell, IBM, SUN, and others, and he is credited for some of
the advanced features in the recent products of NCR, COMPAQ, Virtual,
MainStreetNetworks, and others). His work is referenced extensively in SCI
(over 100 times), plus in numerous conference papers and university
textbooks (he is the most referenced author in several well known books of
the major USA publishers, by authors from Stanford, Harvard, Boston, MIT,
etc). His current research is in infrastructure (software systems and
related hardware accelerators) for e-business on the Internet. He served
on the Scientific Advisory Boards of several start-ups in the USA, and is
the General Chair of the successfull series of SSGRR conferences in
L'Aquila near Rome, Italy. He is a Fellow of the IEEE.

Shubu Mukherjee is a Senior Staff Hardware Engineer in VSSAD, Intel
Corporation. His interests include fault-tolerant processors and
high-performance interconnection networks. In the past, he worked for
Digital Equipment Corporation for ten days and Compaq for over three years,
where he was involved with the design and development of the Alpha 21364
network architecture and fault-tolerant techniques for future Alpha
processors. Currently, he co-directs the FACT (Fault Aware Computing
Technology) project with Dr. Joel Emer.  He has an MS and PhD from the
University of Wisconsin-Madison and B.Tech. from the Indian Institute of
Technology, Kanpur.

Dimitris Nikolopoulos is an Assistant Professor
of Computer Science at the College of William&Mary.
Prior to joining William&Mary, he was a Visiting
Assistant Professor of the Coordinated Science Laboratory
at the University of Illinois, Urbana-Champaign and a research
associate of the High Performance Computing Laboratory at the
University of Patras in Greece. He received a Ph.D.
in Computer Engineering in 2000 and a Diploma in Computer
Engineering in 1996, both from the University of Patras.
His primary research interest is the integration of system software
components to simplify concurrent programming and provide performance
portability across the entire spectrum of high-end computing systems.
He has authored more than 35 technical publications in prestigious international
journals and conferences, including three publications that won Best
Paper Awards at Supercomputing'2000, IPDPS'2002 and CCGrid'2002.

Ramón Beivide received a BSc degree in Computer Science from the Universidad Autónoma de Barcelona in 1981 and a PhD degree also in Computer Science from the Universidad Politécnica de Catalunya (UPC) in 1985. He has been an assistant professor at the Universidad Politécnica de Catalunya and at the Universidad del País Vasco both in Spain. In 1991, he joined the School of Telecommunication Engineering at Universidad de Cantabria, Spain, where he is currently a professor.  His research interests include parallel computers, interconnection systems, performance evaluation and graph theory. Dr. Beivide has published around 100 technical papers and he has served as referee, editor and program chair of different international magazines and conferences. Dr. Beivide is a member of the IEEE Computer society.