Daniel Angel Jiménez is a doctoral candidate in the Department of
Computer Sciences at the University of Texas at Austin.  He received
bachelors and masters degrees in Computer Science from the University
of Texas at San Antonio.  His main research interests are in dealing
with the technology tradeoffs that affect high performance computing.

Wolfgang Karl holds a position as Senior Scientist at the Department
of Computer Science, Technische Universität München. Currently he also
holds a temporary professorship at the University of Karlsruhe.

Wolfgang Karl received a Ph.D. in Computer Science in 1992 from the
Technische Universität München, Department of Computer Science. His
research interests comprise computer architecture, especially parallel
processing, cluster computing, and microprocessor designs.

Doug Burger is an Assistant Professor in Computer Sciences at the
University of Texas at Austin.  He received his Ph.D. in Computer
Sciences from the University of Wisconsin-Madison very late in 1998.
His main research interests are in computer architecture and its
many affiliated areas, and he is co-leader of the TRIPS project at
UT-Austin.

Peter Hsu received the Ph.D. degree in Computer Science from the
University of Illinois at Urbana-Champaign in 1985.  His thesis
topic was compiler technology for VLIW architectures.
His Bachelor degree is from the University of Minnesota in 1979.

From 1985 to 1987 he was with IBM T. J. Watson Research Center
in Yorktown, New York, where he worked on the code generator
of the RS/6000 compiler.  He then joined Cydrome, a startup
company that developed a VLIW machine.  That company became
financially unviable and he joined the Advanced Development
department of Sun Microsystems in 1988, where he worked on a
gallium arsinide implementation of Sparc.

From 1990 to 1997 Peter was with Silicon Graphics Computer
Systems.  He was chief architect and manager of the MIPS R8000
("TFP") microprocessor.  Deployed in the 18-way Power Challenge
multiprocessor server in 1994, his product propelled SGI to
become a major player in the scientific computing market.
He also managed a 3-D graphics project at SGI.

In 1997 Peter co-founded ArtX, a 3-D graphics company best
known for designing the Nintendo GameCube video console.
ArtX has since been acquired by ATI Technologies.  From 1999
to 2001 he was with Toshiba America, where he developed
a CAD methodology for a fully synthesizable standard cell
embedded superscalar processor.

Peter is currently a self-employed consultant.  He recently
spent a semester at the University of Wisconsin in Madison,
researching new techniques for out-of-order execution.
He is interested in all areas of computer design,
from hardware circuit design to software technology, from
the purely technical to the marketing of computing devices.

Oskar Mencer is currently a Member of Technical Staff at Bell Labs in Murray Hill,
and part-time at Imperial College in London. He received his Ph.D. and M.S. in
Electrical Engineering from Stanford University in 2000 and1997 respectively,
and a B.S. degree in Computer Engineering from the Technion/Israel in 1994.
His research Interests span computer architecture, computer arithmetic,
VLSI microarchitecture, CAD and reconfigurable (custom) computing.
More specifically, he is interested in improving the programmability of FPGAs
and making the compute power of reconfigurable computers accessible to the
computer science community.

Dr Cristina Cifuentes is a researcher and principal investigator
of the Walkabout project at Sun Microsystems Labs, California.  She
was formerly an Associate Professor at the University of Queensland,
Australia, where she researched in the areas of binary translation,
decompilation, and legal aspects of computing.  She received a PhD in
Computer Science from the Queensland University of Technology in 1995.
Cristina was the General Chair of the Working Conference on Reverse
Engineering 2000, and has served in the Program Committee of several
conferences and workshops.  Currently, she is the Chair of the IEEE
Technical Committee on Software Engineering's Reverse and Reengineering
Committee.  Cristina is a member of the ACM and the IEEE Computer
Society.  She can be reached at cristina.cifuentes@eng.sun.com

Ron Perrott is currently Professor of Software Engineering in the School of
Computer Science at the Queen's University of Belfast.  He has a long established
and well-documented record of research in the areas of software engineering,
programming languages and operating systems which is detailed in over 150
scientific papers.  In addition, he has authored/edited five books on these topics.

Dr Perrott's research interests are based on languages, algorithms and tools for
multi-processor and distributed computers.  This work was started when he was
employed at the NASA Ames Research Center in California in the 1980s where he
worked on a software system for the world's first supercomputer, the Illiac 4.
His current research interests are in the area of grid middleware and its application.

Dr Perrott lectures world-wide and contributes to many international conference
committees in the area of information technology.  In the UK he is a member of
several research council committees and panels.  In particular, he is currently
Chairman of the UK's Technology Watch Panel for High Performance Computing
and the EU Monitoring Panel.

Enric holds a PhD in Computer Science from the Polytechnic
University of Catalonia since 1996. He joined National
Semiconductor Corp./Cyrix in that year to micro-architect
embedded and high-performance x86 processors. In 1999
he joined XStream Logic (currently named Clearwater Networks)
to develop a class of network processors for layers 4-7.
His research interests are in low-power micro-architectures
and high-level synthesis techniques for low power.

Sanjay is an Assistant Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. He is a
recipient of a 2001 NSF CAREER Award. He recieved his PhD from the University of Michigan, Ann Arbor in 1999. He is co-author
(with Yale N. Patt) of a unique bottom-up introduction to computing titled "Introduction to Computing Systems: from bits and gates to C
and beyond." His research interests include processor microarchitcture, computer architecture, and high performance and reliable
computer systems. He received a BS and a MS from the University of Michigan and has done hardware verification, logic design, and
performance modelling at Digital Equipment Corporation, Intel, and HAL Computer Systems, and has consulted for Transmeta and Jet
Propulsion Laboratory.

Ricardo Baeza-Yates was born in March, 21st, 1961 at Santiago de Chile. He started his electrical engineering studies at the
University of Chile in 1979, finishing with the highest degree in January of 1985, and obtaining the award ``Marcos Orrego Puelma"
given by the Institute of Engineers of Chile to the best student of each year. During the same time he pursued the B.Sc. & M.Sc. in
Computer Science ending also in 1985. His thesis concerning the analysis of algorithms on search trees, generated several
publications. The same year he joined the Computer Science department of the University of Chile as a lecturer. In 1986 he obtained
the M.Eng. degree on Electronics (Digital Systems) with a thesis on computer graphics. That year he started his Ph.D. studies at the
University of Waterloo, Canada, which were finished in 1989. During that time he obtained several scholarships from the province of
Ontario, the Institute for Computer Research, the Information Technology and Research Centre, and the Univ. of Waterloo. He
finished his courses with an average grade of 98%. His Ph.D. thesis was done under the supervision of Gaston Gonnet, and working
on the project which computarized the Oxford English Dictionary. The specific topic was algorithms for text searching, and the results
of the thesis generated several journal and conference papers. After that, he held a post-doctoral fellowship for six months before
coming back to the Dept. of Computer Science at the Univ. of Chile.

In 1990 he was promoted to the associate professor level and from 1990 to 1991 he was in charge of the M.Sc. program in Computer
Science. As a teacher, he has introduced several new courses on key technologies, including computer graphics (1985), graphical
interfaces over X-windows (1990), and object orientation (1991). During this period he continued to do research on algorithms, text
retrieval, program animation, and graphical interfaces. Under his guidance, several students have obtained the engineering or M.Sc.
degree in computer science. He has obtained several research grants from the National Research Council (CONICYT), private
institutions and the government of Spain, closely working with researchers in Brazil, Canada, France, Spain, United States, and
Venezuela. He has been visiting professor or invited speaker at several places all around the world, as well as referee of several
journals, conferences, NSF, etc. He is member of the ACM, IEEE, EATCS, SIAM and SCCC.

One of his research projects, jointly with a software house, produced a state-of-the-art text retrieval package for Windows, which
obtained the PC-Magazine prize for the best chilean software in 1992. This software, SearchCity, was mentioned in Byte and
Communications of the ACM, but the lack of marketing capital aborted this endevour.

In 1992 he was elected president of the Chilean Computer Science Society (SCCC) for a two year period. During 1993, he was
elected chairman for two years of the CS Dept. at the Univ. of Chile and received the Organization of American States (OAS) prize
for young researchers in science. During 1994 he received an award from the Institute of Engineers of Chile for the best engineering
research trajectory of the past 5 years. He was also reelected as president of the SCCC, position that he held until October of 1995,
being reelected again in November of 1996. In April of 1995 was promoted to Full Professor and in September of that year finished
his period as chairman. During 1996 he was in sabbatical at the Univ. Politecnica de Catalunya and in 1997 jointly with Eduardo
Barbosa and Nivio Ziviani won the Compaq Prize to the best brazilian research article in basic CS.

In the professional side, he has been Consultant to the National Identification Bureau on imaging technology (1995-2000), on CS
education to IBM (1994), on computer architecture to Sonda (DEC distributor in Chile, 1995) and for the Informatization Project of the
National Congress (1991-92). He has also been Consultor of IOM (International Organization for Migrations, UN) for the analysis of
the Information System of the Chilean National Congress (1990). Also technical assesor for a mid-range computer equipment survey
in Chile conducted by Langton-Clarke (1990); and design assesor in several software development projects and commercial
systems.

Ronny Ronen is the director of the Microarchitecture Research, Intel Labs
in the Intel Israel Design Center. The research group focuses on promoting
microarchitecture innovations to improve performance and reduce power of
future Intel IA32 processor generations. In the past, the group focused on
microarchitecture innovations for high performance - including topics like
ILP improvements, enhanced instruction caching structures, and more.

Prior to his microarchitecture activities, Ronny led the Pentium®
Processor compiler and performance simulation activities in the Intel
Israel Software department (in Haifa). Before that he was involved in
various software projects, most notably the development of software
development tools for the 8051 microcontroller, leading the hosting of
Intel tools on the VAX/VMS environment, leading the iRMX-286 R2.0 OS
development, and leading the development of i860 software development
tools.

Ronny received his B.Sc. and M.Sc. degrees in Computer Science from the
Technion, Israel Institute of Technology, in 1978 and 1979 respectively.
Ronny is an Intel Principal Engineer and a senior member of the IEEE.

Robert is a Senior Member of Technical Staff in the VSSAD group at Compaq,
where he works on advanced compiler technology for Alpha microprocessors. He
joined DIGITAL in 1992, and has implemented profile-feedback and trace
scheduling in the backend of the product compilers and OM post link
optimizer. At Digital and Compaq, Robert has been a key contributor to
Spike, a post link optimizer for NT and Unix. He has spent the past year
working on a joint project with Ericsson, developing compilers for
telecommunication systems. Robert received a B.A. from Cornell University
and a Ph.D. in computer science from Carnegie Mellon University.

Uri Weiser received his B.Sc and M.Sc degrees in Electrical Engineering from
the Technion, Israel Institute of Technology, Haifa, Israel in 1970 and 1975
respectively. He received his Ph.D in Computer Science from the University
of Utah, Salt Lake City, in 1981.

Dr. Weiser joined Intel's Israel Design Center in 1988. His first initiative
was the Pentium® processor concept definition, feasibility study and
performance simulator. As the Director of Platform Architecture Center in
Santa Clara, Calif., (1991-1992), Uri led Intel's Microprocessor Roadmap
activity. Uri became the Director of the Israeli Microprocessor Architecture
Group in 1993 and drove the definition of Intel's MMX technology
architecture. Uri's Microarchitecture research resulted in the "Trace-Cache"
concept, "Streaming data concepts", "Dynamic tuning", and others. During
1999-2001 Uri Co-Managed the Intel's newly formed Texas Development Center,
Austin, Texas. Uri leads today a new Streaming Processing initiative at
Intel.

Prior to his career at Intel, Dr. Weiser worked for the Israeli Department
of Defense (RAFAEL) from 1970 to 1984, as Research and System Engineer. His
next position was with National Semiconductor Design Center, Israel from
1984 to 1988, leading the design of National's NS32532 Microprocessor.

Dr. Weiser became an Intel Fellow in 1996 and got the IEEE Fellow title in
2002 "for contributions to Computer Architecture".  Dr. Weiser holds an
Adjunct Professor position at the Technion IIT, he is an Associate Editor of
IEEEMicro Magazine and of Architecture Letters. Uri was member of the
Technical Committee and Session chair in numerous conferences, including
International Symposium of Computer Architecture (ISCA), Hot Chips,
CompEuro, MICRO, and ICCD. He held invited lectures at several Universities,
among them: Stanford, MIT, Caltech, Univ. of Texas, University of Utah,
Technion, and UCLA.

Guri Sohi teaches computer architecture
at the University of Wisconsin-Madison.  He joined
the Wisconsin faculty after receiving his Ph.D from
the University of Illinois in 1985, and is currently
a Professor in both the Computer Sciences and Electrical
and Computer Engineering departments.

Sohi's research has been in the area of architectural
and microarchitectural techniques for high-performance
microprocessors, including instruction-level parallelism,
out-of-order execution with precise exceptions, non-blocking caches,
decentralized microarchitectures, speculative multithreading,
and memory dependence speculation.  He received the
1999 ACM SIGARCH Maurice Wilkes award for
contributions in the areas of high issue rate
processors and instruction level parallelism.

Ph.D. SUNY-Stony Brook, 1977. Professor Hennessy initiated the MIPS project at Stanford in 1981,
 MIPS is a high- performance Reduced Instruction Set Computer (RISC), built in VLSI. MIPS was
 one of the first three experimental RISC architectures. In addition to his role in the basic research,
 Hennessy played a key role in transferring this technology to industry. During a sabbatical leave from
 Stanford in 1984-85, he cofounded MIPS Computer Systems (now called MIPS Technologies Inc.),
 which specializes in the production of chips based on these concepts. He also led the Stanford
 DASH (Distributed Architecture for Shared Memory) multiprocessor project. DASH was the first
 scalable shared memory multiprocessor with hardware-supported cache coherence. Most recently,
 he has been involved in FLASH (FLexible Architecture for Shared Memory), which is designed to
 support different communication and coherency approaches in large-scale shared-memory
 multiprocessors. Hennessy is also the coauthor of two widely used textbooks in computer
 architecture.

Doctoral degree from the University of Pavia, Italy: Founder and Manager of
computational chemistry departments : Large Scale Scientific Computations (at
IBM Research, San José, California, 1960-72); Calcolo Chimico (Istituto
Donegani, Montedison, Novara, Italy, 1974-78); Scientific and Engineering
Computations (IBM Poughkeepsie and IBM Kingston, New York, 1979-91); Chimica
Computazionale (CRS4, Cagliari, 1991-1994), Laboratoire METECC, University L.
Pasteur, Strasbourg (1992-present). Lecturer : Edward Herbert Boomer Memorial
(Alberta, 1980), Bourke (RSC-Faraday Society, 1982). Distinguished Research
Professor, Rennselear Polytechnic Institute, Troy, New York (1984). IBM Fellow
(1969) and Fellow of the American Physical Society (1985); Member of the
Academia degli Agiati (1972), IBM Academy of Technology (1989), President of
International Society of Quantum Biology (1981). Gold medals : TERESIANA
(University of Pavia, 1984) and DIRAC (World Association of Theoretical Organic
Chemistry, 1987), Founder and President of the "Club Europeén MOTECC" doctor
Honoris causae, University of N.D.P, Namur (Belgium) (1999), Alexander von
Humboldt Award winner (2001)
Author of:

 Over 400 scientific papers: Editor of the MOTECC and METECC series. Author of
"Tables of Atomic Functions" IBMJ Res. and Dev. Special Supplement 9, 2, 1965.
Author, with C. Roetti, of "Tables of Roothaan-Hartree-Fock Wavefunctions",
Special Issue in "Atomic Data and Nuclear Data Tables", Academic Press, New
York, 1974.

Important Contributions:
  Pioneering (1961-68) ab initio quantum chemistry applications to large
molecular systems and coding of Hartree-Fock atomic and molecular programs.
First systematic estimate of correlation energy for atoms and molecules.
Pioneering (1963) density functionals methods for atoms and molecules. Atomic
and Molecular relativistic correction (since early sixties, to present).
Pioneering graphics. Pioneering (1979) Monte Carlo and Molecular Dynamics for
biological systems in aqueous solutions with ab initio potentials for liquid
water and solutions (with G. Corongiu) and codes. Pioneering combined use of
Newton and Schrodinger equations in classical molecular dynamics (1978). Free
distribution of atomic, molecular, Monte Carlo and Molecular Dynamic codes.
Pioneering (1983) parallel architecture and construction of LCAP1, LCAP2 and
LCAP-3090 hardware and relative system software with applications to quantum
chemistry and molecular dynamics.

Paolo Ienne was born in 1965 in Milano, Italy.

He obtained the title of Dottore in Ingegneria Elettronica from the Politecnico di Milano in 1991. In 1990-91, he has been a junior
researcher at Brunel University, Uxbridge, Great Britain where he worked on testability analysis and functional fault simulation.

From 1992 to 1996 he has been a research assistant at the Microcomputing Laboratory (LAMI) and at the MANTRA Centre for
Neuro-Mimetic Systems of the Swiss Federal Institute of Technology of Lausanne (EPFL) where he completed his Ph.D. thesis on
Programmable VLSI Systolic Processors for Neural Network and Matrix Computations. He lectured on hardware for neural
networks and on general-purpose parallel architectures.

In December 1996 he has joined Siemens AG in the Semiconductors Group in Munich, Germany which became on 1st April 1999
Infineon Technologies AG. After some research work on datapath generation tools, he headed the embedded memory unit in the
Design Libraries division. The unit supplied almost all Infineon logic designers with SRAM and ROM memory generators and, at
some point, DSP processor cores. Active researches in the unit addressed advanced memory architectures, state-of-the-art
characterization of very complex blocks, and generation and synthesis of arithmetic components.

Since July 2000 he is a professor at the Swiss Federal Institute of Technology of Lausanne (EPFL) and he heads the Processor
Architecture Lab (LAP).

His research interests include computer and processor architecture, language-based VLSI design flows, computer arithmetic,
systolic array processors, hardware for neural networks, and design for testability.

El Dr Chung-Jen (CJ) Tan actualment és el director de l'E-Business
Technology Institute (ETI) a l'universitat de Hong Kong (HKU).
Anteriorment va ser Senior Manager al departament de Application
Systems Technologies a IBM T.J. Watson Research Center a Nova York.

Doug Burger has been an assistant professor of Computer Sciences and
Electrical & Computer Engineering at the University of Texas at Austin
since 1999.  He received his B.S.  from Yale University and his
Ph.D. from the University of Wisconsin-Madison.  His main research
interest is computer architecture, and his other interests are
compiler design, operating systems, and distance running.  He has
recently been named a Sloan Foundation Research Fellow, an NSF CAREER
Award winner, an IBM University Partnership Program recipient, and a
Texas Excellence Teaching Award winner.

Undergraduate studies at the Techincal University of Lisbon, Portugal
(Computer and Electronics Engineering, 1992). Graduate studies at the
University of Illinois at Urbana-Champaign, U.S.A. (M.Sc. and Ph.D. in
Computer Science, 1995 and 1998 respectively).
He has worked at IBM T.J. Watson Research Center, U.S.A. as a
Researcher (1997), at the University of Illinois at Urbana-Champaign,
U.S.A. as a Visiting Scholar (2000) and  at Intercollege Limassol as
an Assistant Professor (1998-2001). Since January 2002 he is a member
of the faculty of the Department of Computer Science of the University
of Cyprus.
His research interests include computer architecture with a focus on
the memory hierarchy, architecture-aware optimizations for database
workloads, advanced memory technologies and power-aware optimizations.

Dr. Luiz Andre Barroso is a Senior Software Engineer at Google Inc.,
where he works on performance optimizations for Google's search
engine infrastructure. Before joining Google, he was a Senior Member of
the Research Staff at Compaq and Digital Equipment Corporations, where
he and his colleages published several influential papers in computer
architecture and processor design for database and web server
workloads. At Compaq, he also co-architected and designed the Piranha
chip-multiprocessor system. Dr. Barroso's current interests include
large-scale clustering systems, web and database server performance,
and processor/memory system design. He holds B.S. and M.Sc.
degrees in Electrical Engineering from PUC University, Rio de Janeiro,
as well as M.S. and Ph.D. degrees in Computer Engineering from USC,
Los Angeles.

David Kaeli received his B.S. in Electrical Engineering
from Rutgers University, his M.S. in Computer Engineering from
Syracuse University, and his PhD in Electrical Engineering from
Rutgers University.  He is currently an Associate Professor
on the faculty of the Department of Electrical and Computer Engineering
at Northeastern University.  Prior to 1993, he spent 12 years at IBM,
the last 7 at IBM T.J. Watson Research in Yorktown Heights, N.Y..
In 1996 he received an NSF CAREER Award.  He currently directs
the Northeastern University Computer Architecture Research Laboratory
(NUCAR).  Dr. Kaeli's research interests include computer architecture and
organization, compiler optimization, VLSI design, trace-driven simulation
and workload characterization.  He is a member of the IEEE and ACM.
He is presently an Associate Editor for IEEE Transactions on Computer and
IEEE Computer Architecture Letters.