Yale Patt is Professor of Electrical and Computer Engineering and the Ernest Cockrell, Jr. Centennial Chair
in Engineering at the University of Texas at Austin.

He enjoys equally teaching freshmen, teaching graduate students, and directing the research of nine PhD students in high performance computer implementation. He has, for more than 30 years, combined an active research program with extensive consulting and a strong commitment to teaching.

The focus of his research is generally five to ten years beyond what industry provides at that point in time. His rationale has always been that he does not do revenue shipments, preferring to produce knowledge that will be useful to future revenue shipments and, more importantly, graduates who will design those future products.

In 1965, Yale Patt introduced the WOS module, the first complex logic gate implemented on a single piece of silicon ["A complex logic module for the synthesis of combinatorial switching circuits," Proceedings of the 1967 Spring Joint Computer Conference, Atlantic City, April, 1967]. In 1984, he (and his students Wen-mei Hwu, Steve Melvin, and Mike Shebanow) introduced HPS, a high performance microarchitecture that exploits instruction level paralelism by combining wide-issue (fetching and issuing multiple instructions each cycle), aggressive dynamic branch prediction, dynamic scheduling, out-of-order execution, and checkpoint in-order retirement (enabling precise exceptions). The first two papers describing this work, "HPS, A New Microarchitecture: Rationale and Introduction" and "Critical Issues Regarding HPS, A High Performance Microarchitecture," were presented at Micro-18, and published in the Proceedings of the 18th Microprogramming Workshop, Asilomar, CA, December, 1985. In 1991 he (and his student Tse-Yu Yeh) introduced the Two-Level Branch Predictor, which provided much greater accuracy than was available before that. The paper, "Two-Level Adaptive Branch Prediction," was presented at Micro-24, and published in the Proceedings of the 24th International Symposium and workshop on Microarchitecture, Albuquerque, November, 1991.

Today, Yale Patt works on problems for the microprocessors of the year 2009, when technology promises each chip will contain a billion transistors. Two of his current activities are the Trace Cache, where instruction sequences are stored in physical order corresponding to their logical order, and Subordinate Simultaneous Microthreading, a variation of Simultaneous Multithreading that is particularly useful in sequential threads of control.

Much as he enjoys research, Professor Patt's first love is teaching. The focus of his teaching has always been on understanding the fundamentals. At Michigan, he overhauled the introductory computer organization course, the intensive computer design course, and most recently (with his former colleague Kevin Compton) EECS 100, the first required computing course for undergraduate EE, CS, and CE majors. Their bottom-up approach is the subject of his new textbook, "Introduction to Computing Systems, From Bits and Gates to C and Beyond," McGraw-Hill, ISBN: 0-07-237690-2. It is co-authored with his former PhD student Sanjay Patel, who is now an Assistant Professor at the University of Illinois, Urbana-Chapaign. The first edition will be available from the publisher, August 15, 2000.

He has also taught more than 5000 engineers in industry, in IEEE conference tutorials and in short courses at company sites.

Yale Patt earned his BS at Northeastern University and his MS and PhD at Stanford University, all in electrical engineering. He received the 1995 IEEE Emannuel R. Piore Medal "for contributions to computer architecture leading to commercially viable high performance microprocessors," the 1996 IEEE/ACM Eckert -Mauchly Award "for important contributions to instruction level paralelism and superscalar processor design," and the 1999 IEEE Wallace W. McDowell Award "for your impact on the high performance microprocessor industry via a combination of important contributions to both engineering and education."
He is a Fellow of the IEEE.

For his teaching, he was named "Outstanding Professor of the Year," by the Michigan Chapter of Eta Kappa Nu in 1992. He received the Teaching Excellence Award of the EECS Department at Michigan in 1995 and the College of Engineering of Michigan in 1996. In 1998, he was named an Arthur F. Thurnow professor at Michigan for his commitment to undergraduate education. He recently was named the National ACM Lectureship Progam's Outstanding Lecturer of the Year, 1998-99.

University of Valenciennes, FRANCE
 

Smail NIAR is professor in  computer science at the university of Valenciennes in France.
He obtained his Ph.D. degree in computer science from the university of Lille (France) in 1990.
The project consisted of designing and simulating highly efficient network of processors
dedicated to declarative languages (such as Prolog and ML).
His interest topics are:

• Micro-architecture:  Multithreading and Trace Cache
• Parallel Algorithms in combinatorial optimization: Parallel meta-heuristics, and parallel multiple alignment of biological sequences.

In addition of his research and teaching, Smail NIAR is in charge of the "Maîtrise d´informatique"
equivalent to the MSc. degree. Smail NIAR likes to discuss and to exchange ideas with students and
other researchers in his fields of interest.
 

DAC, UPC

Juanjo Noguera obtained his degree in computer sciences from Universitat Autonoma de Barcelona, in 1997.
From September 1997 until June 2000, he worked at the Spanish National Center for Microelectronics
(CNM-CSIC), where he was involved with VHDL design, and rapid system prototyping. Currently,
Juanjo Noguera is an assistant professor at the Dept. of Computer Architecture (DAC-UPC).
He is also a PhD student, and his main research field is HW/SW codesign techniques for dynamically
reconfigurable architectures.

Intel

Doug Carmean is a principal architect with the Desktop Products Group in
Oregon. Doug was one of the key architects, responsible for definition of
the Intel® Pentium® 4 Processor. Doug has been with Intel for 11 years,
working on iA32 processors spanning from the 80486 through the generation
beyond the Intel Pentium 4. Prior to joining Intel, Doug did hard time at
ROSS Technology, Sun Microsystems, Cypress Semiconductor and Lattice
Semiconductor. Doug enjoys fast cars and scary, Italian motorcycles.

Vice President of Product Development, BOPS Inc.
 

Dr. Baker has 20 years of industry experience, including key roles at TI,
IBM, Brooktree, Compaq and Equator. His areas of expertise include hardware
and software product development in PC graphics, audio, video, imaging, and
digital TV. Dr. Baker successfully developed and brought to market many
products, and as Vice President of System Engineering at Equator
Technologies, he helped to develop a system-on-silicon chip solution for the
digital TV market place. Dr. Baker received his MS and Ph.D. degrees from
the University of Texas at Austin in 1979 and 1989, respectively.

Department of Information and Computer Sciences
Nara Women's University, JAPAN

Kazuki Joe received the B.S. degree in mathematics from Osaka
University in 1984, M.S. and PhD degree in information science from
Nara Institute of Science and Technology in 1995 and 1996
respectively. He is currently a professor at Nara Women's University.
rom 1984 to 1986, he was a software engineer of Japan DEC.  From 1986
to 1990, he was a researcher of ATR Auditory and Visual Perception
Research Lab.  From 1991 to 1993, he was a senior researcher of Kubota
corporation.  From 1996 to 1997, he was an assistant professor at Nara
Institute of Science and Technology.  From 1998 to 1999, he was an
associate professor at Wakayama University.  His research interests
include parallel computer architectures, analytic modeling for
parallel computers, parallelizing compilers, neural networks and image
processing.  He is the chair of IPSJ SIGMPS (Information Processing
Society Japan, SIG Mathematical Modeling and Problem Solving).

Intel Microprocessor Research Labs.

Ronny Ronen is the manager of the Microarchitecture Research Lab of MRL in the Intel Israel Design Center.
The  research group focuses on promoting microarchitecture innovations to improve performance and reduce
power of future Intel IA32 generations. Past research in the group focused on microarchitecture innovations
for high performance and included topics like ILP improvements, enhanced instruction caching structures, and more.

Prior to his microarchitecture activities, Ronny led the Pentium® Processor compiler and performance simulation
activities in the Intel Israel Software department (in Haifa). Before that he was involved in various software projects,
most notably the development of software development tools for the 8051 microcontroller, leading the hosting of
Intel tools on the VAX/VMS environment, leading the iRMX-286 R2.0 OS development, and leading the development
of i860 software development tools.

Ronny received his B.Sc. and M.Sc. degrees in Computer Science from the Technion, Israel Institute of Technology,
in1978 and 1979 respectively. Ronny holds five patents and has published five papers. Ronny is an Intel Principal
Engineer and a senior member of the IEEE.

 ACSEL Director, ECE Dept.,
 University of California Davis

Prof. Vojin G. Oklobdzija, obtained Ph.D. in Computer Science from the University of California, Los Angeles in 1982, MSc
degree in 1978 and Dipl. Ing. (MScEE) from the Electrical Engineering Department, University of Belgrade, Yugoslavia in 971.

From 1982 to 1991 he was at the IBM T.J.Watson Research Center in New York where he worked on  development of RISC
architecture and processors and super-scalar RISC, IBM RS/6000 (PowerPC) in particular, on which he co-holds a patent
on Register-Renaming. This technique enabled the entire generation of super-scalar processors and is used in every
high-performance processor today.

From 1988-90 he was visiting faculty at the University of California Berkeley while on leave from IBM.  Since 1991 Prof.
Oklobdzija has held various consulting and academic positions. He was consultant to Sun Microsystems Laboratories, AT&T
Bell Laboratories, Hitachi Research Laboratories, Silicon Systems Inc. and Siemens Corp. where he was principal architect
for the new generation of embedded logic and memory processors. Currently he is advisor to SONY and Fujitsu Laboratories.
Prof. Oklobdzija has academic appointment with the University of California and various visiting academic appointments. As a
Fulbright professor he was lecturing at the universities in South America. In 1991 he spent time in Peru and Bolivia as a
Fulbright Professor developing academic programs in South America. During 1996-98 he taught courses in the Silicon Valley
through the University of California Berkeley Extension and Hewlett-Packard.

Prof. Oklobdzija holds five U.S., five European, one Japan and one Taiwan patents and eight other US patents currently
pending. He is a Fellow of IEEE and a member of American Association of the University Professors. He serves on the
editorial boards of the Journal of VLSI Signal Processing and IEEE Transaction of VLSI Systems and as a program
committee member of the International Solid-State Circuits Conference. He was a General Chair of the 13th Symposium on
Computer Arithmetic, Vice Chair at the International Conference on Computer Design, organizer of 2001 Microprocessor
Design Workshop and program committee member of the International Symposium on VLSI Technology. He has published
over 120 papers and has given over 100 invited talks and short courses in the USA, Europe, Latin America, Australia, China
and Japan
 

HP Labs, Palo Alto
 

Dejan Milojicic is a senior scientist at Hewlett-Packard Laboratories,
where he leads a kernel internals group. He has worked in the areas of
operating systems and distributed systems for almost 20 years. He is
a chair of the IEEE TCOS and on the editorial board of IEEE Distributed
Systems Online. He received his BS and MS in electrical engineering
from the University of Belgrade, Yugoslavia, and his PhD in computer
science from the University of Kaiserslautern, Germany.

Contact him at Hewlett Packard Labs, MS 3U-18, 1501 Page Mill Rd., Palo Alto,
CA 94304; dejan@hpl.hp.com; www.hpl.hp.com/personal/Dejan_Milojicic.

University of Washington

Jean-Loup Baer received a Diplome d'Ingenieur in Electrical
Engineering and a Doctorat 3e cycle in Computer Science from the
Universite de Grenoble (France) and a Ph.D. from UCLA in 1968.

He is Professor of Computer Science and Engineering and Adjunct Professor of
Electrical Engineering at the University of Washington, where he has been since 1969.
He was Chair of the Department of  Computer Science and Engineering from 1998 till 1993.
His present research interests are in computer systems architecture with a concentration
on the design and evaluation of memory hierarchies, and in parallel and distributed
processing. He is the author of the textbook "Computer Systems Architecture"
and of about 100 refereed papers. He has supervised 21 Ph.D. students.

Baer has served as an ACM National Lecturer and was an IEEE Computer Science
Distinguished Visitor. He is a Guggenheim Fellow, an ACM Fellow and an IEEE Fellow.
Baer has held several Editorial positions and has served as General Chair and
Program Chair of several conferences including ISCA and HPCA.

Centre for Advanced Studies, IBM Toronto Lab

Dr. Zuzarte is with IBM at the Toronto Labs working as manager in the Rewrite
and Optimizer development team.

Yiannakis Sazeides was born in Nicosia, Cyprus. He received the BS
degree from Oakland University, Rochester, Michigan,
in 1991 in the area of Computer Engineering and the ME degree in
Electrical Engineering from Cornell University, New York, in May 1992.
He held a lecturer position with the Department of Computer Sciences
and Engineering at Intercollege, Cyprus, for the 1992-93 academic
year. Yanos was awarded a PhD degree in August 1999 from the
University of Wisconsin, Madison in Electrical Engineering. For most
of 1999 he was with the Alpha Development Group (Compaq-USA) where he
contributed to the research and development of the next generation
alpha processor. As of January 2000 Yanos is a visiting professor with
the Department of Computer Science at the University of Cyprus. His
main research interests lie in the area of Computer Architecture with
particular emphasis on instruction level parallelism, high performance
microprocessors, program behavior, novel execution paradigms,
prediction, speculation and multithreading.

University of Illinois at Urbana-Champaign

José Fernando Martínez obtuvo los títulos de Diplomado y Licenciado en
Informática por la Universidad Politécnica de Valencia en 1994 y 1996,
recibiendo del Ministerio de Educación el primer y tercer Premio Nacional de
Terminación de Estudios, respectivamente. Le fue adjudicada entonces
una Beca de Ampliación de Estudios en el Extranjero del Banco de España,
con la que marchó a la Universidad de Illinois en Urbana-Champaign, donde
obtuvo el título de Master en Computer Science en enero de 1999, y donde
cursa estudios de doctorado en la actualidad. José ha trabajado en el
Instituto de Astrofísica de Canarias, en Cray Research, y también en IBM
Thomas J. Watson Research Centre.

University of Wisconsin, Madison

Guri Sohi teaches computer architecture
at the University of Wisconsin-Madison.  He joined
the Wisconsin faculty after receiving his Ph.D from
the University of Illinois in 1985, and is currently
a Professor in both the Computer Sciences and Electrical
and Computer Engineering departments.

Sohi's research has been in the area of architectural
and microarchitectural techniques for high-performance
microprocessors, including instruction-level parallelism,
out-of-order execution with precise exceptions, non-blocking caches,
decentralized microarchitectures, speculative multithreading,
and memory dependence speculation.  He received the
1999 ACM SIGARCH Maurice Wilkes award for
contributions in the areas of high issue rate
processors and instruction level parallelism.

University of Wisconsin-Madison

Miron Livny received a B.Sc. degree in Physics and Mathematics in 1975
from the Hebrew University and M.Sc. and Ph.D. degrees in Computer
Science from the Weizmann Institute of Science in 1978 and 1984, respectively.
Since 1983 he has been on the Computer Sciences Department faculty at the
University of Wisconsin-Madison, where he is currently a Professor of Computer Sciences.

Dr. Livny's research focuses on High Throughput Computing, Grid Computing,
and data visualization environments. His recent work includes the Condor high
throughput computing system, the DEVise data visualization and exploration
environment, the ZOO experiment management framework, quality controlled
lossy image compression, and data clustering.

IBM T. J. Watson Research Center
 

Marc Snir received a Ph.D. in Mathematics, from the Hebrew University of
Jerusalem, in 1979. He worked at NYU on the NYU Ultracomputer project in
1980-1982, and worked at the Hebrew University of Jerusalem from1982 to
1986, when he joined the IBM T. J. Watson Research Center.
At IBM he headed research that led to the line of high performance IBM SP
systems, led research on various areas of high-performance computing and
high-end server systems and  initiated and led the Blue Gene project. Marc
Snir has published over 100 journal and conference papers on computational
complexity, parallel algorithms, parallel architectures, and parallel
programming, coauthored the MPI standard and contributed to other
languages, libraries and tools for parallel programming.
Marc is on the editorial board of Transactions on Computer Systems and
Parallel Processing Letters.
He is member of the IBM Academy of Technology, ACM Fellow and IEEE Fellow.

Centre for Advanced Studies, IBM Toronto Laboratory
 

Marin Litoiu received a Ph.D. in  System Control  in 1995 with Polytechnic
University of Bucharest (UPB). He was member of the faculty of the
Department of Computers and Control Systems of the UPB and he held research
visiting positions with Polytechnic of Turin (1994 and 1995) and
Polytechnic University of Catalunia, European Center for Parallelism(1995).
In 1999, he got another Ph.D. degree from Carleton University, Canada, in
Performance Engineering.

His research interests include performance modeling and evaluation on
distributed and real time systems, distributed objects and Internet
technologies.

Currently, Dr. Litoiu is with Center for Advanced Studies at IBM Toronto Lab.